Hybrid integration of III-V devices with Silicon-based waveguides (Si, SiN, SiO2)
Hélène Debrégeas, Almae Technologies, France
Lucas Soldano, POET Technologies, USA
22.09.2022, 10:45 – 12:30
The model of photonic devices has been evolving from standard packaging to photonic integrated circuits with more efficient and low-cost coupling solutions, compatible for ultra-dense integration. Multiple developments have been done on photonic integrated circuits, either fully on InP platforms mainly for active devices (lasers, high-speed modulators, photodiodes, …), or with Silicon Photonics (passive devices, high-speed modulators, photodiodes, …). But to make the best of both platforms in terms of performances and economic model, many laboratories or companies develop hybrid integration of III-V materials and Silicon-based devices (with Si, SiN, or SiO2 waveguides).
This workshop will focus on the solutions for this hybrid integration, and will present the different technologies to couple light from III-V material to Si-based waveguides. Firstly, heterogeneous integration where III-V lays directly on top of Si-based waveguides with evanescent coupling. Secondly hybrid integration, where the III-V device is butt-jointed to Si-based waveguides, with various alignment techniques and waveguiding approaches. Thirdly, it will present emerging technologies still in development, their challenges and potential, such as transfer printing or direct growth in Si.
The comparison will not only be on the technical / performances point of view, but as well on the business aspects, by analysing the business model, versatility and compatibility with multiple suppliers or external foundries, process tolerance to improve yield and costs. Presenters will explain what drove their choices, what are their main applications today and how they foresee future evolutions.
10:50: Hybrid integration of III-V materials with silicon for high-volume and high-reliability lasers and optical amplifiers, Haisheng Rong, Intel, USA
11:10: An overview on thick-SOI Silicon Photonic platforms and integration roadmap at VTT, Giovanni Delrosso, VTT, Finland
11:30: Hybrid Integration Platform for Co-Packaged Photonics Using POET’s CMOS Based Optical Interposer, Suresh Venkatesan, POET Technologies, USA
11:50: Hybrid integration of III-V semiconductors on silicon, Dries Van Thourhout, Ghent University - IMEC, Belgium
Speaker 1: Scott Schube, Intel, USA
Title: Hybrid integration of III-V materials with silicon for high-volume and high-reliability lasers and optical amplifiers
Biography: Scott has worked in the optical communications component industry for 20 years in both technical and marketing roles. As an engineer he developed Gigabit Ethernet transceivers for AMP Lytel and then at Tyco Subcom he designed high-performance receiver line cards for ultra-longhaul undersea communication. Scott went on to a variety of marketing and management roles, from technical marketing to product management and strategic marketing, at Intel OPD and NeoPhotonics, as well as senior analyst at optics industry research firm LightCounting. Currently Scott is senior director of strategic marketing and business development in Intel’s silicon photonics group, where he has helped grow the business from zero to one of the leading global optical transceiver suppliers.
Speaker 2: Giovanni Delrosso, VTT Technical Research Centre of Finland, Finland
Title: An overview on thick-SOI Silicon Photonic platforms and integration roadmap at VTT
Abstract: Silicon photonics (SiPh) is progressively unveiling its best as the most successful and versatile technology platform able to converge optical and microelectronic functionalities into a Silicon chip, whose fabrication process may even differ from the Complementary Metal–Oxide–Semiconductor (CMOS) foundry mainstream. As an example of versatility, VTT’s thick-SOI technology offers a reliable alternative with its micron-scale cross-section waveguides (WGs), lower propagation loss (~0.1 dB/cm), reduced polarization sensitivity, and suitability to handle higher optical power without exciting nonlinear losses. Enabling efficient edge and mirror couplings, thick-SOI is becoming a preferred solution in large-bandwidth optical transceivers, wearable health monitoring devices as well as an emerging solution for superconducting quantum computing operating at cryogenic temperatures. In this contribution, we provide emphasis on a sustainable hybrid and heterogeneous integration roadmap of active devices performed at wafer level (WLP), with the aim to significantly reduce packaging costs while improving testability and reliability.
Biography: Mr. Giovanni Delrosso is a Sr. Scientist and Project Mgr. at VTT (Finland), developing wafer level packaging for Silicon Photonics and Quantum devices. He earned more than 35 years of experience in Photonic Packaging with primary R&D centers and enterprises, exploiting innovative E/O interconnection technologies among USA, EMEA and Brazil. Prior VTT, he was Sr. Adv. Packaging & Integration Architect at GigOptix Inc. (USA),) and Sr. Researcher at CPqD Foundation (Brazil). From 1986 to 2010 he joined Pirelli Labs (Italy), pioneering Optical Amplifiers and Tunable Lasers. He holds a Dipl-E.E.in Electronics, and he is inventor in 15 granted patents.
Speaker 3: Suresh Venkatesan, POET Technologies, USA
Title: Hybrid Integration Platform for Co-Packaged Photonics Using POET’s CMOS Based Optical Interposer
Abstract: Dr. Suresh Venkatesan will present a unique hybrid integration platform for wafer scale passive assembly of electronics and photonics devices using a CMOS based optical interposer. The POET Optical Interposer enables seamless communications between electronics and photonics chips that are assembled on standard 200 or 300mm silicon wafers using visually assisted passive flip chip bonding techniques. This unique integration platform is the first such platform in the industry adapted to directly modulated lasers and enables the world’s smallest single chip Transmit/Receive Optical engine for 100G-400G optical engines.
Biography: Dr. Suresh Venkatesan is currently the Chairman & CEO of POET Technologies, Inc. Prior to joining POET Technologies in 2015, Dr. Venkatesan was SVP and CTO at GlobalFoundries, where he grew the 28 nm business from zero to $2B, and set the foundation for its 14 nm technology strategy. His 20+ years of semiconductor experience included many director of technology development and foundry roles within Freescale and Motorola. While at Motorola, he received three High Impact Technology awards and was inducted into the Scientific Advisory Board Associates (SABA). At Freescale, he was nominated as a Freescale Fellow. In 2017, he received the Outstanding Alumni award from Purdue University’s Electrical Engineering department for his contributions to the field of Semiconductor Technology. Dr. Venkatesan holds over 50 U.S. patents, and has co-authored over 50 technical papers. He has a Bachelor’s of Technology in Electrical Engineering degree from the Indian Institute of Technology (1987), and an MSEE (1988) and PhD (1992), both from Purdue University.
Speaker 4: Dries Van Thourhout, Ghent University - IMEC, Belgium
Title: Hybrid integration of III-V semiconductors on silicon
Abstract: In this presentation, I will focus on emerging and exploratory integration approaches for hybrid integration of III-V semiconductors on silicon. These will include transfer printing and recent results on direct epitaxial growth of III-V on silicon. I will shortly introduce techniques such as planar quantum dot growth, TASE, Aspect Ratio Trapping and Nanoridge engineering and comment on their scalability and promises for integration with already developed waveguide platforms.
Biography: Dries received the Ph.D. degree from Ghent University in 2000. From Oct. 2000 to Sep. 2002 he was with Lucent Technologies, Bell Laboratories, New Jersey, USA. In Oct. 2002 he joined the photonics research group at Ghent University - IMEC. His main topics involve Silicon nanophotonic devices and the integration of novel materials (III-V, graphene, ferro-electrics, quantum dots, ...) on these waveguides. He has submitted 14 patents and authored over 270 journal papers. He is member of the IEEE Photonics Society, SPIE and OSA (fellow). He received both an ERC Starting Grant (ULPPIC) and ERC Advanced Grant (NARIOS). He received the prestigious "Laureaat van de Vlaamse Academie Van Belgie" prize in 2012.